Native switching of variable-length packets

Problem

For high-speed networks, memory speed limits output buffered and shared memory switch architectures to low port densities. Recent work demonstrates that input buffered ATM switches with virtual output queueing and suitable input-output matching algorithms can achieve high throughputs. Can these algorithms be extended to input buffered switches and repeaters that use variable length packets? Can these switches be made stable with a minimum of internal speed-up? Is a bounded delay achievable?

Objectives

Our objectives are to advance new algorithms for achieving high throughput in input-buffered Ethernet switches and in full-duplex repeaters. We will study the application of traffic shaping and scheduling algorithms to enable QoS support in input buffered switches. We will also demonstrate that these methods can be used to provide simultaneous best-effort and guaranteed rate with bounded delay service in Gigabit Ethernets.

Work completed

We have completed developing simulation models of output queued (OQ), input queued (IQ), and combined input and crossbar queued (CICQ) switches. We have modeled PIM, iSLIP, RR/RR, OPF/RR, and other scheduling algorithms.

Work in progress

None. This part of the project is complete.

Results

The following papers and letters have been published:

See the publications page.

The following simulation models and hardware descriptions are available:

See the simulation models page for models.
See the miscellaneous page for hardware descriptions.

This material is based upon work supported by the National Science Foundation under grant No. 9875177. Any opinions, findings and conclusions or recommendations expressed in this material are those of the author and do not necessarily reflects the views of the National Science Foundation (NSF).

Last updated by Ken Christensen on DECEMBER 20, 2003